ISL6174IRZ【PDF 13/16 页】IC CIRC BREAKER DUAL LV 28-QFN

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Sheet目录40

9页 10页 11页 12页 [13页]14页 15页 16页

FN6830.0

December 19, 2008

Figure 22 illustrates the GATE response time to an output

short. The time from the input current > 2.2A (I

) to the

FET gate being pulled down is ~0.6祍.

The previous scope shots illustrate the performance with a

~18ms circuit breaker delay, t

as determined by the

10.5礔 cap on TCB pin. Figure 23 shows the performance

with an open TCB pin for the same amplitude of OC event as

shown in Figure 19. Once again, see the TCB pin ramp

duration and t

of ~3祍, the intrinsic delay of the IC OC

response.

Dual Voltage Tracking During Turn-on

The ISL6174 Dual Circuit Breaker is also designed to

provide either concurrent or ratiometric tracking of the two

output voltages during turn-on. This capability is critical in

providing power to many high value loads.

The two channels can be forced to track each other by

simply tying their SS pins together and using a common SS

capacitor, C

. In addition, their EN

pins also must be tied

together. Typical Start-up waveforms in this mode are shown

in Figure 24, where the common C

value is 0.066礔.

If one channel experiences a CB event and turns off, the

other one will too.

To achieve ratiometric tracking, the ratio of the two C

must

match the ratio of the two voltages being handled. In the

illustrated case in Figure 25, the 1.5V to 3.3V ratio of 1:2.2 is

FIGURE 21. WOC CIRCUIT BREAKER OPERATION ZOOM

GATE

TCB

Iin

FIGURE 22. SHORTED OUTPUT GATE RESPONSE

GATE

Iin

FIGURE 23. TRANSIENT TO 3.9A OC CIRCUIT BREAKER

OPERATION with TCB OPEN

GATE

TCB

Iin

FIGURE 24. CONCURRENT TRACKING MODE

ISL6174

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